
Distance-scaling fault tolerance of the three-sheet multiplexed FCC
sheet code at L = 4, 6, 8
Raghu Kulkarni
1
1
SSMTheory Group, IDrive Inc., Calabasas, CA 91302, USA , raghu@idrive.com
Abstract
We provide a circuit-level numerical validation of the three-sheet time-multiplexed FCC
sheet code [
2
], a quantum low-density parity-check (qLDPC) construction with parameters
[[3
L
3
,
6
L, L
]] derived from the three triad sheets of the face-centered cubic lattice. At
L
= 4
the code packs 24 logical qubits into 192 data qubits at distance 4, an encoding rate of 12.5%,
higher than any other published code at this distance. Three independent sheet-codes share
one chip; ancillas are shared, stabilizers are extracted in three sequential rounds, and the
inactive sheets accumulate depolarizing noise during each round at rate 2
p
. We simulate
the full circuit-level memory experiment with explicit CNOT cascades, depolarizing noise on
every gate, and minimum-weight perfect matching decoding via PyMatching [
3
] on Stim’s [
4
]
detector error model. Threshold under the multiplex idle penalty falls between 0.4% and
0.5%, in agreement with [
2
]. Distance scaling is sharp: the per-logical error rate suppresses
by Λ(4
→
6) = 11
.
2 between consecutive even
L
at
p
= 0
.
001, and Λ(6
→
8) = 7
.
8. At
L
= 8
the [[1536
,
48
,
8]] code achieves a per-logical error rate of 5
.
9
×
10
−5
, more than an order of
magnitude below the physical rate, on a 48-logical-qubit memory. These suppression factors,
measured in simulation deeply sub-threshold, are over five times those recently reported on
noisy hardware [
5
] on a single-logical surface-code memory; an apples-to-apples comparison
at matched operating point requires either future hardware experiments on this code or a
surface-code simulation at the same deeply sub-threshold operating point and is not made
here. The natural hardware target is the
L
= 6 instance: [[648
,
36
,
6]] encodes 36 logical qubits
at distance 6 in 864 physical qubits, fitting Atom Computing’s 1180-qubit Phoenix processor
and exceeding every prior multi-logical hardware demonstration in distance and logical-qubit
count. The
L
= 4 instance overlaps with Atom Computing and Microsoft’s 24-logical [[4
,
2
,
2]]
demonstration [
8
], providing a calibration point at quadrupled distance (
d
= 4 vs
d
= 2) and
full error correction in place of error detection.
Keywords: quantum error correction, qLDPC codes, FCC sheet code, time-multiplexed
measurement, fault-tolerant scaling, neutral-atom quantum computing
1 Introduction
Surface codes [
6
] dominate the quantum-error-correction landscape because they pair a high
circuit-level threshold (
∼
1%) with a planar layout requiring only nearest-neighbor connectivity.
Their cost is rate: a distance-
d
rotated surface code encodes one logical qubit in
∼
2
d
2
physical
qubits, and the qubit overhead per logical scales as
d
2
. Recent qLDPC constructions, notably
IBM’s bivariate-bicycle (BB) family [
7
], demonstrate that this overhead can be reduced; the
[[144
,
12
,
12]] BB code packs 12 logicals at distance 12 into 144 qubits, at the cost of weight-6
stabilizers and a non-planar layout. Google’s Willow processor [
5
] recently demonstrated below-
threshold fault tolerance on the surface code with Λ
≈
2
.
14 across distances 5 through 7, but the
experiment encoded only one logical qubit.
Reference [
2
] introduces the FCC sheet code, an alternative qLDPC construction obtained by
restricting a face-centered cubic stabilizer code [
1
] to a single triad sheet. The single-sheet code
1